DC3 — FPGA-Based AI Accelerator Options for Ultra-Low-Carbon Inference
Host: École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland — Embedded Systems Laboratory (ESL).
Work package: WP1 (Programmable Energy-Integrated Infrastructure)
Duration and start: 36 months, full-time; start between February and September 2027 (latest start September 2027).
The project
Standard AI chips such as GPUs are built for peak speed, not for the wide range of power levels that grid services need. In this project you design a flexible AI accelerator whose power use can switch at runtime.
You will extend the open-source X-HEEP platform from EPFL with switchable power modes, and target two real AI applications: visual quality inspection in factories, and AI-driven radio-network optimization for telecom.
What you will work on:
- Design carbon-aware hardware with flexible accelerator modes.
- Build a compiler and runtime that schedule work across the CPU and a Coarse-Grained Reconfigurable Array (CGRA) based on carbon signals.
- Produce “energy model cards” that record latency, energy, and the cost of switching states.
What you will deliver:
- FPGA prototypes benchmarked for performance and energy against a GPU baseline, for both applications.
- A grid-interactive accelerator shown to change its power in real time.
Secondments
You will spend two research visits with partners in the network:
- Technical University of Denmark (DTU) (Lyngby, Denmark) — 3 months from around September 2028 (academic), with Xenofon Fafoutis: work with the neural-architecture-search project to tune the accelerator configurations for AI-model deployment.
- Ericsson (Finland) — 3 months from around September 2029 (industry), with Miika Komu: test the accelerator’s performance on realistic data.
The host
The Embedded Systems Laboratory (ESL) at EPFL works on system-level design for energy-efficient computing, from the chip to the datacenter, and leads the open hardware platform X-HEEP.
Supervision
Main supervisor: David Atienza (ORCID) — Full Professor and Head of the Embedded Systems Laboratory, EPFL; IEEE and ACM Fellow. He works on energy-efficient computing from the chip to the datacenter and leads the open X-HEEP platform.
Co-supervisors:
Profile we are looking for
- Digital hardware design (FPGA / RTL) and computer architecture
- Compilers or runtime systems are a plus
- Some background in AI or machine learning is helpful
- MSc (completed or near completion) in electrical or computer engineering, or a related field
- Curiosity, initiative, and good spoken and written English
You must also meet the MSCA eligibility rules — no PhD yet, the mobility rule, and open to all nationalities.
How to apply
Official vacancy at the host institution: link coming soon.
Until then, apply through the central AEGIS application portal: AEGIS application portal (reference position DC3), and read what to include in your application.
Questions about this position? Contact the coordinator, Prof. Paul Pop, aegis@compute.dtu.dk.